1. Field of the Invention
The present invention relates generally to methods for forming dielectric layers within integrated circuits. More particularly, the present invention relates to methods for forming planarized low dielectric constant dielectric layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device dimensions have decreased and integrated circuit device densities have increased, it has become increasingly important to form within advanced integrated circuits patterned interconnecting conductor layers which exhibit reduced delay times. Patterned interconnecting conductor layers which exhibit reduced delay times are desirable within advanced integrated circuits since reduced delay times within advanced integrated circuits typically provide: (1) apparent reductions in advanced integrated circuit operating speed; (2) deceases in patterned interconnecting conductor layer cross-talk; and (3) decreases in advanced integrated circuit power dissipation.
In order to reduce patterned interconnecting conductor layer delay time within advanced integrated circuits, it is known in the art of advanced integrated circuit fabrication to employ when forming inter-metal dielectric (IMD) layers between adjoining or successive patterned conductor layers within advanced integrated circuits dielectric materials which have a comparatively low dielectric constant. Within the general categories of dielectric materials which may be employed when forming inter-metal dielectric (IMD) layers within integrated circuits, organo-functional siloxane polymer dielectric materials are, in general, known to possess comparatively lower dielectric constants (ie: typically in the range of from about 1.8 to about 3.9) in comparison with purely inorganic dielectric materials such as silicon oxide dielectric materials, silicon nitride dielectric materials silicon oxynitride dielectric materials (ie: which typically have dielectric constants in the range of from about 2.8 to about 5.0). Such organo-functional siloxane polymer dielectric materials are known in the art of integrated circuit fabrication as a sub-group of gap-filling spin-on-glass (SOG) dielectric materials. They may be formed into inter-metal dielectric (IMD)) layers within advanced integrated circuits through spin-on-glass (SOG) coating and curing methods. In contrast, dielectric layers which are formed from purely inorganic dielectric materials are typically, although not exclusively, formed within advanced integrated circuits through activated deposition methods such as but not limited to thermal chemical vapor deposition (CVD) methods, plasma enhanced chemical vapor deposition (PECVD) methods and physical vapor deposition (PVD) sputtering methods.
Although organo-functional siloxane polymer dielectric materials are thus desirable as low dielectric constant dielectric materials when forming inter-metal dielectric (IMD) layers within advanced integrated circuits, organo-functional siloxane polymer dielectric materials are not entirely without problems in forming inter-metal dielectric (IMD) layers within advanced integrated circuits. In particular, it is known in the art of integrated circuit fabrication that intermetal dielectric (IMD) layers formed from organo-functional siloxane polymer dielectric materials are generally more difficult to reproducibly planarize through conventional chemical mechanical polish (CMP) planarizing methods than are otherwise equivalent inter-metal dielectric (IMD) layers formed from purely inorganic silicon oxide dielectric materials, silicon nitride dielectric materials or silicon oxynitride dielectric materials, since organo-functional siloxane polymer dielectric materials typically have relatively lower chemical mechanical polish (CMP) planarizing rates in comparison with purely inorganic silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials. In addition, inter-metal dielectric (IMD) layers formed from organo-functional siloxane polymer dielectric materials when planarized through conventional chemical mechanical polish (CMP) planarizing methods typically also provide planarized organo-functional siloxane polymer inter-metal dielectric (IMD) layers with less uniformly planar surfaces than analogous inter-metal dielectric (IMD) layers formed from purely inorganic silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials.
It is thus desirable within the art of microelectronics fabrication, such as but not limited to advanced integrated circuit microelectronics fabrication, to provide chemical mechanical polish (CMP) planarizing methods through which low dielectric constant organo-functional siloxane polymer dielectric materials may be formed and planarized to provide planarized organo-functional siloxane polymer dielectric layers, such as but not limited to planarized organo-functional siloxane polymer inter-metal dielectric (IMD) layers, with increased chemical mechanical polish (CMP) planarizing rates and with enhanced chemical mechanical polish (CMP) planarizing uniformity. It is towards these goals that the present invention is directed.